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C/C++ Source or Header  |  2000-04-04  |  12KB  |  367 lines
  1. /***************************************************************************
  2.  
  3. Driver by Manuel Abadia <manu@teleline.es>
  4.  
  5. Gaelco Game list:
  6. =================
  7.  
  8. 1987:    Master Boy
  9. 1991:    Big Karnak, Master Boy 2
  10. 1992:    Splash!**, Thunder Hoop, Squash
  11. 1993:    World Rally*, Glass**
  12. 1994:    Strike Back, Target Hits*, Thunder Hoop 2
  13. 1995:    Alligator Hunt, Mechanical Toy***, World Rally 2*, Salter, Touch & Go
  14. 1996:    Maniac Square****, Snow Board**, Speed Up (3D)
  15. 1997:    Surf Planet (3D)
  16. 1998:    Radikal Bikers (3D), Bang
  17. 1999:    Rolling Extreme (3D)
  18. 2000:    Football Power* (3D)
  19.  
  20. (*)        Created by Zigurat Software
  21. (**)    Created by OMK Software
  22. (***)    Created by Zeus Software
  23. (****)    Created by Mandragora Soft
  24.  
  25. All games newer than Splash are heavily protected:
  26.     World Rally, Squash, Thunder Hoop (and probably others) have encrypted Video RAM.
  27.     World Rally (and probably others) has a protected MCU.
  28.  
  29.  
  30. ============================================================================
  31.                             SPLASH!
  32. ============================================================================
  33.  
  34. Splash! memory map:
  35. -------------------
  36. 0x000000-0x03ffff    ROM (m68000 code + graphics)
  37. 0x100000-0x3fffff    ROM (graphics)
  38. 0x800000-0x83ffff    Screen 2    (pixel layer                (512x256))
  39. 0x840000-0x840001    Dipsw #1
  40. 0x840002-0x840003    Dipsw #2
  41. 0x840004-0x840005    Input #1
  42. 0x840006-0x840007    Input #2
  43. 0x84000e-0x84000f    Sound command
  44. 0x880000-0x880fff    Screen 0    (8x8 tiles        64x32        (512x256))
  45. 0x881000-0x8817ff    Screen 1    (16x16 tiles    32x32        (512x512))
  46. 0x881800-0x881801    Screen 0 scroll registers
  47. 0x881802-0x881803    Screen 1 scroll registers
  48. 0x881804-0x881fff    Work RAM (1/2)
  49. 0x8c0000-0x8c0fff    Palette (xRRRRxGGGGxBBBBx)
  50. 0x900000-0x900fff    Sprite RAM
  51. 0xffc000-0xffffff    Work RAM (2/2)
  52.  
  53. Interrupts:
  54.     Level 6 INT generated by VBLANK
  55.  
  56. Unmapped addresses in the driver:
  57.  
  58. 0x84000a-0x84000b\
  59. 0x84001a-0x84001b |    These registers seems to be used by the time
  60. 0x84002a-0x84002b |    measurement system for coin detector
  61. 0x84003a-0x84003b/
  62.  
  63. 0x84007a-0x84007b    Set to 0 when clearing the pixel layer.
  64.                     After that is set to 0xffff.
  65.  
  66.  
  67. In the Z80, what does $e000 do?
  68.  
  69. ***************************************************************************/
  70.  
  71. #include "driver.h"
  72. #include "vidhrdw/generic.h"
  73. #include "cpu/z80/z80.h"
  74. #include "cpu/m68000/m68000.h"
  75.  
  76. extern unsigned char *splash_vregs;
  77. extern unsigned char *splash_videoram;
  78. extern unsigned char *splash_spriteram;
  79. extern unsigned char *splash_pixelram;
  80.  
  81. /* from vidhrdw/gaelco.c */
  82. READ_HANDLER( splash_vram_r );
  83. READ_HANDLER( splash_pixelram_r );
  84. WRITE_HANDLER( splash_vram_w );
  85. WRITE_HANDLER( splash_pixelram_w );
  86. int splash_vh_start( void );
  87. void splash_vh_screenrefresh( struct osd_bitmap *bitmap,int full_refresh );
  88. WRITE_HANDLER( paletteram_xRRRRxGGGGxBBBBx_word_w );
  89.  
  90.  
  91. static WRITE_HANDLER( splash_sh_irqtrigger_w )
  92. {
  93.     if ((data & 0x00ff0000) == 0)
  94.     {
  95.         soundlatch_w(0,data & 0xff);
  96.         cpu_cause_interrupt(1,Z80_IRQ_INT);
  97.     }
  98. }
  99.  
  100.  
  101. static struct MemoryReadAddress splash_readmem[] =
  102. {
  103.     { 0x000000, 0x3fffff, MRA_ROM },            /* ROM */
  104.     { 0x800000, 0x83ffff, splash_pixelram_r },    /* Pixel Layer */
  105.     { 0x840000, 0x840001, input_port_0_r },        /* DIPSW #1 */
  106.     { 0x840002, 0x840003, input_port_1_r },        /* DIPSW #2 */
  107.     { 0x840004, 0x840005, input_port_2_r },        /* INPUT #1 */
  108.     { 0x840006, 0x840007, input_port_3_r },        /* INPUT #2 */
  109.     { 0x880000, 0x8817ff, splash_vram_r },        /* Video RAM */
  110.     { 0x881800, 0x881803, MRA_BANK1 },            /* Scroll registers */
  111.     { 0x881804, 0x881fff, MRA_BANK2 },            /* Work RAM */
  112.     { 0x8c0000, 0x8c0fff, paletteram_word_r },    /* Palette */
  113.     { 0x900000, 0x900fff, MRA_BANK3 },            /* Sprite RAM */
  114.     { 0xffc000, 0xffffff, MRA_BANK4 },            /* Work RAM */
  115.     { -1 }
  116. };
  117.  
  118. static struct MemoryWriteAddress splash_writemem[] =
  119. {
  120.     { 0x000000, 0x3fffff, MWA_ROM },                                        /* ROM */
  121.     { 0x800000, 0x83ffff, splash_pixelram_w, &splash_pixelram },            /* Pixel Layer */
  122.     { 0x84000e, 0x84000f, splash_sh_irqtrigger_w },                            /* Sound command */
  123.     { 0x880000, 0x8817ff, splash_vram_w, &splash_videoram },                /* Video RAM */
  124.     { 0x881800, 0x881803, MWA_BANK1, &splash_vregs },                        /* Scroll registers */
  125.     { 0x881804, 0x881fff, MWA_BANK2 },                                        /* Work RAM */
  126.     { 0x8c0000, 0x8c0fff, paletteram_xRRRRxGGGGxBBBBx_word_w, &paletteram },/* Palette */
  127.     { 0x900000, 0x900fff, MWA_BANK3, &splash_spriteram },                    /* Sprite RAM */
  128.     { 0xffc000, 0xffffff, MWA_BANK4 },                                        /* Work RAM */
  129.     { -1 }
  130. };
  131.  
  132.  
  133. static struct MemoryReadAddress splash_readmem_sound[] =
  134. {
  135.     { 0x0000, 0xd7ff, MRA_ROM },                    /* ROM */
  136.     { 0xe800, 0xe800, soundlatch_r },                /* Sound latch */
  137.     { 0xf000, 0xf000, YM3812_status_port_0_r },        /* YM3812 */
  138.     { 0xf800, 0xffff, MRA_RAM },                    /* RAM */
  139.     { -1 }
  140. };
  141.  
  142. static int adpcm_data;
  143.  
  144. static WRITE_HANDLER( splash_adpcm_data_w ){
  145.     adpcm_data = data;
  146. }
  147.  
  148. static void splash_msm5205_int(int data)
  149. {
  150.     MSM5205_data_w(0,adpcm_data >> 4);
  151.     adpcm_data = (adpcm_data << 4) & 0xf0;
  152. }
  153.  
  154.  
  155. static struct MemoryWriteAddress splash_writemem_sound[] =
  156. {
  157.     { 0x0000, 0xd7ff, MWA_ROM },                    /* ROM */
  158.     { 0xd800, 0xd800, splash_adpcm_data_w },        /* ADPCM data for the MSM5205 chip */
  159. //    { 0xe000, 0xe000, MWA_NOP },                    /* ??? */
  160.     { 0xf000, 0xf000, YM3812_control_port_0_w },    /* YM3812 */
  161.     { 0xf001, 0xf001, YM3812_write_port_0_w },        /* YM3812 */
  162.     { 0xf800, 0xffff, MWA_RAM },                    /* RAM */
  163.     { -1 }
  164. };
  165.  
  166.  
  167. INPUT_PORTS_START( splash )
  168.  
  169. PORT_START    /* DSW #1 */
  170.     PORT_DIPNAME( 0x0f, 0x0f, DEF_STR( Coin_A ) )
  171.     PORT_DIPSETTING(    0x06, DEF_STR( 5C_1C ) )
  172.     PORT_DIPSETTING(    0x07, DEF_STR( 4C_1C ) )
  173.     PORT_DIPSETTING(    0x08, DEF_STR( 3C_1C ) )
  174.     PORT_DIPSETTING(    0x09, DEF_STR( 2C_1C ) )
  175.     PORT_DIPSETTING(    0x0f, DEF_STR( 1C_1C ) )
  176.     PORT_DIPSETTING(    0x05, DEF_STR( 2C_3C ) )
  177.     PORT_DIPSETTING(    0x0e, DEF_STR( 1C_2C ) )
  178.     PORT_DIPSETTING(    0x0d, DEF_STR( 1C_3C ) )
  179.     PORT_DIPSETTING(    0x0c, DEF_STR( 1C_4C ) )
  180.     PORT_DIPSETTING(    0x0b, DEF_STR( 1C_5C ) )
  181.     PORT_DIPSETTING(    0x0a, DEF_STR( 1C_6C ) )
  182.     PORT_DIPSETTING(    0x00, "1C/1C or Free Play (if Coin B too)" )
  183.     PORT_DIPNAME( 0xf0, 0xf0, DEF_STR( Coin_B ) )
  184.     PORT_DIPSETTING(    0x60, DEF_STR( 5C_1C ) )
  185.     PORT_DIPSETTING(    0x70, DEF_STR( 4C_1C ) )
  186.     PORT_DIPSETTING(    0x80, DEF_STR( 3C_1C ) )
  187.     PORT_DIPSETTING(    0x90, DEF_STR( 2C_1C ) )
  188.     PORT_DIPSETTING(    0xf0, DEF_STR( 1C_1C ) )
  189.     PORT_DIPSETTING(    0x50, DEF_STR( 2C_3C ) )
  190.     PORT_DIPSETTING(    0xe0, DEF_STR( 1C_2C ) )
  191.     PORT_DIPSETTING(    0xd0, DEF_STR( 1C_3C ) )
  192.     PORT_DIPSETTING(    0xc0, DEF_STR( 1C_4C ) )
  193.     PORT_DIPSETTING(    0xb0, DEF_STR( 1C_5C ) )
  194.     PORT_DIPSETTING(    0xa0, DEF_STR( 1C_6C ) )
  195.     PORT_DIPSETTING(    0x00, "1C/1C or Free Play (if Coin A too)" )
  196.  
  197. PORT_START    /* DSW #2 */
  198.     PORT_DIPNAME( 0x03, 0x03, DEF_STR( Difficulty ) )
  199.     PORT_DIPSETTING(    0x02, "Easy" )
  200.     PORT_DIPSETTING(    0x03, "Normal" )
  201.     PORT_DIPSETTING(    0x01, "Hard" )
  202.     PORT_DIPSETTING(    0x00, "Hardest" )
  203.     PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Lives ) )
  204.     PORT_DIPSETTING(    0x08, "1" )
  205.     PORT_DIPSETTING(    0x04, "2" )
  206.     PORT_DIPSETTING(    0x0c, "3" )
  207.     /*     according to the manual, Lives = 0x00 is NOT used */
  208.     PORT_DIPNAME( 0x10, 0x10, DEF_STR( Demo_Sounds ) )
  209.     PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
  210.     PORT_DIPSETTING(    0x10, DEF_STR( On ) )
  211.     PORT_DIPNAME( 0x20, 0x20, "Girls" )
  212.     PORT_DIPSETTING(    0x00, "Light" )
  213.     PORT_DIPSETTING(    0x20, "Hard" )
  214.     PORT_DIPNAME( 0x40, 0x40, "Paint Mode" )
  215.     PORT_DIPSETTING(    0x00, "Paint again" )
  216.     PORT_DIPSETTING(    0x40, "Normal" )
  217.     PORT_SERVICE( 0x80, IP_ACTIVE_LOW )
  218.  
  219. PORT_START    /* 1P INPUTS & COINSW */
  220.     PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_PLAYER1 )
  221.     PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_PLAYER1 )
  222.     PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER1 )
  223.     PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_PLAYER1 )
  224.     PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
  225.     PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
  226.     PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
  227.     PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
  228.  
  229. PORT_START    /* 2P INPUTS & STARTSW */
  230.     PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP    | IPF_8WAY | IPF_PLAYER2 )
  231.     PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN  | IPF_8WAY | IPF_PLAYER2 )
  232.     PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_PLAYER2 )
  233.     PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT  | IPF_8WAY | IPF_PLAYER2 )
  234.     PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
  235.     PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
  236.     PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 )
  237.     PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
  238. INPUT_PORTS_END
  239.  
  240.  
  241. #define TILELAYOUT8(NUM) static struct GfxLayout tilelayout8_##NUM =    \
  242. {                                                                        \
  243.     8,8,                                    /* 8x8 tiles */                \
  244.     NUM/8,                                    /* number of tiles */        \
  245.     4,                                        /* bitplanes */                \
  246.     { 3*NUM*8, 1*NUM*8, 2*NUM*8, 0*NUM*8 }, /* plane offsets */            \
  247.     { 0,1,2,3,4,5,6,7 },                                                \
  248.     { 0*8,1*8,2*8,3*8,4*8,5*8,6*8,7*8 },                                \
  249.     8*8                                                                    \
  250. }
  251.  
  252. #define TILELAYOUT16(NUM) static struct GfxLayout tilelayout16_##NUM =                \
  253. {                                                                                    \
  254.     16,16,                                    /* 16x16 tiles */                        \
  255.     NUM/32,                                    /* number of tiles */                    \
  256.     4,                                        /* bitplanes */                            \
  257.     { 3*NUM*8, 1*NUM*8, 2*NUM*8, 0*NUM*8 }, /* plane offsets */                        \
  258.     { 0,1,2,3,4,5,6,7, 16*8+0,16*8+1,16*8+2,16*8+3,16*8+4,16*8+5,16*8+6,16*8+7 },    \
  259.     { 0*8,1*8,2*8,3*8,4*8,5*8,6*8,7*8, 8*8,9*8,10*8,11*8,12*8,13*8,14*8,15*8 },        \
  260.     32*8                                                                            \
  261. }
  262.  
  263.  
  264. TILELAYOUT8(0x020000);
  265. TILELAYOUT16(0x020000);
  266.  
  267.  
  268. #define GFXDECODEINFO(NUM) static struct GfxDecodeInfo gfxdecodeinfo_##NUM[] =        \
  269. {                                                                                    \
  270.     { REGION_GFX1, 0x000000, &tilelayout8_##NUM,0, 128 },                            \
  271.     { REGION_GFX1, 0x000000, &tilelayout16_##NUM,0, 128 },                            \
  272.     { -1 }                                                                            \
  273. }
  274.  
  275. GFXDECODEINFO(0x020000);
  276.  
  277.  
  278.  
  279. static struct YM3812interface ym3812_interface =
  280. {
  281.     1,                        /* 1 chip */
  282.     3000000,                /* 3 MHz? */
  283.     { 40 },                    /* volume */
  284.     { 0 }                    /* IRQ handler */
  285. };
  286.  
  287. static struct MSM5205interface msm5205_interface =
  288. {
  289.     1,                        /* 1 chip */
  290.     384000,                    /* 384KHz */
  291.     { splash_msm5205_int },    /* IRQ handler */
  292.     { MSM5205_S48_4B },        /* 8KHz */
  293.     { 80 }                    /* volume */
  294. };
  295.  
  296.  
  297. static struct MachineDriver machine_driver_splash =
  298. {
  299.     {
  300.         {
  301.             CPU_M68000,
  302.             24000000/2,            /* 12 MHz */
  303.             splash_readmem,splash_writemem,0,0,
  304.             m68_level6_irq,1
  305.         },
  306.         {
  307.             CPU_Z80,
  308.             30000000/8,            /* 3.75 MHz? */
  309.             splash_readmem_sound, splash_writemem_sound,0,0,
  310.             nmi_interrupt,64    /* needed for the msm5205 to play the samples */
  311.         }
  312.     },
  313.     60,DEFAULT_REAL_60HZ_VBLANK_DURATION,
  314.     1,
  315.     0,
  316.  
  317.     /* video hardware */
  318.     64*8, 64*8, { 2*8, 49*8-1, 2*8, 32*8-1 },
  319.     gfxdecodeinfo_0x020000,
  320.     2048, 2048,
  321.     0,
  322.  
  323.     VIDEO_TYPE_RASTER | VIDEO_MODIFIES_PALETTE,
  324.     0,
  325.     splash_vh_start,
  326.     0,
  327.     splash_vh_screenrefresh,
  328.  
  329.     /* sound hardware */
  330.     0,0,0,0,
  331.     {
  332.         {
  333.             SOUND_YM3812,
  334.             &ym3812_interface
  335.         },
  336.         {
  337.             SOUND_MSM5205,
  338.             &msm5205_interface
  339.         }
  340.     }
  341. };
  342.  
  343.  
  344. ROM_START( splash )
  345.     ROM_REGION( 0x400000, REGION_CPU1 )    /* 68000 code + gfx */
  346.     ROM_LOAD_EVEN(    "4g",    0x000000, 0x020000, 0xb38fda40 )
  347.     ROM_LOAD_ODD(    "4i",    0x000000, 0x020000, 0x02359c47 )
  348.     ROM_LOAD_EVEN(    "5g",    0x100000, 0x080000, 0xa4e8ed18 )
  349.     ROM_LOAD_ODD(    "5i",    0x100000, 0x080000, 0x73e1154d )
  350.     ROM_LOAD_EVEN(    "6g",    0x200000, 0x080000, 0xffd56771 )
  351.     ROM_LOAD_ODD(    "6i",    0x200000, 0x080000, 0x16e9170c )
  352.     ROM_LOAD_EVEN(    "8g",    0x300000, 0x080000, 0xdc3a3172 )
  353.     ROM_LOAD_ODD(    "8i",    0x300000, 0x080000, 0x2e23e6c3 )
  354.  
  355.     ROM_REGION( 0x010000, REGION_CPU2 )    /* Z80 code + sound data */
  356.     ROM_LOAD( "5c",    0x00000, 0x10000, 0x0ed7ebc9 )
  357.  
  358.     ROM_REGION( 0x080000, REGION_GFX1 | REGIONFLAG_DISPOSE )
  359.     ROM_LOAD( "13i",    0x000000, 0x020000, 0xfebb9893 )
  360.     ROM_LOAD( "15i",    0x020000, 0x020000, 0x2a8cb830 )
  361.     ROM_LOAD( "16i",    0x040000, 0x020000, 0x21aeff2c )
  362.     ROM_LOAD( "18i",    0x060000, 0x020000, 0x028a4a68 )
  363. ROM_END
  364.  
  365.  
  366. GAME( 1992, splash, 0, splash, splash, 0, ROT0_16BIT, "Gaelco", "Splash!" )
  367.